This invention relates to metallization processes for semiconductor processing and more particularly to processes using xe2x80x9cdamascenexe2x80x9d (or in-laid) metallization.
Metallization for integrated circuits is usually formed by first depositing the metal layer (usually Al or Al alloys) followed by the patterning process (i.e. lithography and etching). This sequence has various short-comings, such as the severe topographies that are generated by the etched metal pattern and the creation of small gaps between the metal lines that are difficult to fill by the subsequent dielectric layer. Metal etching processes also have problems in dimension control, etching residues and corrosion. In addition, plasma etching of some metals, for example Cu, is difficult.
Another way to form the metallization pattern on integrated circuits is to first etch the conductor pattern to form an in-laid pattern (or grooves) into the dielectric layer, then deposit a metal layer to fill the etched grooves in the dielectric. Typically the metal layer not only fills the grooves but also covers the entire semiconductor wafer. Next, the excess metal over the surface of the wafer is removed (except the portion of the metal in the grooves) using either a CMP (chemical mechanical polishing) process or an etchback process. This process will form in-laid conductors in the dielectric layer thus avoiding the issues associated with metal etching and dielectric gap filling. This in-laid metallization process is also called xe2x80x9cdamascene process.xe2x80x9d
Vias are needed to connect different metallization layers. In damascene processes, typically the via holes are formed in the dielectric layer, then the via holes are filled with metal, and then the excess metal over the wafer surface is removed. Such a process is called xe2x80x9cdamascened vias.xe2x80x9d The via formation is then followed either by the standard metallization process or by a damascened conductor layer as described above. Forming the vias and conductors separately has been called a xe2x80x9csingle damascenexe2x80x9d process. A simpler process is to form both the via and the metallization patterns in the dielectric layer, followed by a single metal filling and excess metal removal process. The formation of the vias and conductors together has been called a xe2x80x9cdual damascenexe2x80x9d process.
The xe2x80x9cdual damascenexe2x80x9d process, even though simpler in concept, is more difficult than the xe2x80x9csingle damascenexe2x80x9d in some aspects because both the via and conductor patterns must be etched in the dielectric layer before metal deposition. Performing both etches creates process control difficulties. Thus, it is desirable to develop a dual damascene process in which the via pattern etching process and the metal pattern etching process can be carried out in a manner such that there are no interactions between the two etches.
One approach for implementing a dual damascene interconnect structure has been the use of a multilayered dielectric, such as a SiO2/SiN/SiO2 or SiO2/Al2O3/SiO2 triple layer dielectric structure. The SiN or Al2O3 layer in such an approach acts as an etch stop layer upon which the conductor pattern etch is stopped. An example of a multilayered dielectric structure for use in damascene metallization is disclosed in U.S. Pat. No. 4,789,648 to Chow et al. Such processes using a SiN or Al2O3 layer as an etch stop have several benefits. However, such processes also create several problems.
First, both SiN and Al2O3 are dielectric materials with a high dielectric constant. (SiNxcx9c7.4, Al2O3xcx9c8.5). Thus, utilizing a SiN or Al2O3 layer between the various metal layers will increase the interconnect capacitance. When using SiN, critical dimension control may be difficult because of the plasma etch properties of SiO2 and SiN. Silicon nitride layers generally exhibit larger stress than oxide layers and thus may lead to stress related problems such as voiding and notching of metal lines. Also, the dielectric strength of Al2O3 is usually an order of magnitude less than that of SiO2 and SiN. This might lead to structure integrity problems during device operation. In addition, the resistivity of Al2O3 is about 2 order of magnitude less than SiO2 and SiN. All these factors may lead to large leakage current between the metal lines and cause metal line integrity problems since the metal lines are directly on the Al2O3 or SiN layers.
In general, the prior art processes require at least two types of dielectric and one type of metal. Choosing three materials or more with the desired electrical, chemical, thermal and mechanical properties that are compatible with each other adds complexity to the fabrication process.
Thus, it is desirable to have an alternative process for the fabrication of damascene structures that lessens the problems and difficulties discussed above.
The present invention may be utilized in a single or dual damascene process. In either process, an etch stop layer is deposited above an inter-layer dielectric (ILD) layer. Then, an intra-metal dielectric (IMD) layer is deposited. The in-laid grooves for the damascened conductor are etched into the IMD layer. The bottom of the damascene grooves are formed by the etch stop layer upon which the etch of the IMD layer stops.
In a dual damascene process, the etch stop layer is patterned to be similar to the damascene conductor layer pattern, however, the etch stop layer pattern allows the etch stop layer to be removed from the regions which will subsequently become via regions. In a single damascene process, the etch stop layer pattern may include etch protection over the VV12 regions since the etch stop layer can be conductive as illustrated in this invention.
After the etch stop layer is patterned and the IMD layer is deposited above the patterned etch stop layer, a reverse image of the damascene conductor pattern is photolithographically created upon the IMD layer. The grooves for the in-laid conductor are then etched. In the dual damascene process, this etch etches through the IMD layer and stops upon the etch stop layer. However, the etch continues through the ILD layer in the VV12 regions which are not protected by the etch stop layer. In a single damascene process, the etch for the in-laid grooves stops upon the etch stop layer in all regions including the via regions because the etch stop layer covers the via regions. For both processes, standard damascene techniques may then be used to fill the in-laid grooves with a metallization and to remove this metallization above the grooves.